The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...
Semiconductor Engineering sat down to discuss the verification of RISC-V processors with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ...
The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...
The computing industry has reached a significant milestone with the ratification of the 1.0 RISC-V Vector Specification. This development marks the beginning of a new era in computing efficiency, as ...
Though the RISC-V Summit North America is over, you can peruse the videos of most of the keynotes and sessions here. The list is quite long, so we picked a few and included them in this space, such as ...
The technology driving our world today is increasingly complex. From the latest flashy AI technology like ChatGPT to autonomous cars and satellite launches to the innovations behind our everyday ...
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